1. Field of the Invention
The present invention relates to a timing adjustment circuit for a data transmitting/receiving circuit for transmitting/receiving data between a data transmitting unit and a data receiving unit, between a plurality of devices and circuit blocks in an LSI, between an LSI, between boards and cabinets, and to an LSI and a data transmitting/receiving system with such a timing adjustment circuit, and more particularly relates to a timing adjustment circuit for adjusting the phase relationship between data and clock in such a way that data can be surely transmitted/received between multiplexers for sequentially converting data bit width gradually in a data transmitting circuit which gradually converts input parallel data into serial data, for example, converts input parallel data with bit width of 16 bits and speed of 2.5 Gbps into 8 bit 5 Gbps→4 bit 10 Gbps→2 bit 20 Gbps→1 bit 40 Gbps, using a clock obtained by dividing an internally generated clock.
2. Description of the Related Art
Recently, in computer and communication fields, the amount of information to be processed has increased. In order to cope with this increasing amount of information, data transmitting/receiving speed between LSIs has increased. A CMOS 10 Gbps transceiver was announced in 2002, although it is still under development. After that, attention is focused on the research of the CMOS 40 Gbps transceiver. More particularly, in an area requiring such a high data transfer rate, the most advanced technology is applied. For example, the CMOS 40 Gbps transceiver is being developed assuming a technology at a 0.1 μm or less level. However, in a data transmitting/receiving system requiring a high data transfer rate, an internal LSI clock frequency must be higher. To contrary to the functional improvement of a transistor accompanying fine semiconductor process, its process unevenness has remarkably increased. Conventionally, a timing margin for data reception has been secured by closely allocating blocks between which data is transmitted/received as much as possible by layout contrivance. However, such a method is close to its limit due to the improvement of a data transfer rate and the process unevenness.
FIG. 1 shows an example of the configuration of a data transmitting circuit being one example of the above-described high-speed transceiver. The data transmitting circuit shown in FIG. 1 gradually converts input parallel data into serial data, using a clock obtained by frequency dividers (210, 220 and 230) sequentially dividing a clock internally generated by a PLL (100) after parallel data with width of 16 bits and speed of 2.5 Gbps is once stored in a first-in first-out (FIFO) data buffer 110. Specifically, input data of 16 bit width and 2.5 Gbps is converted into data of 8 bit width and 5 Gbps by a 16:8 multiplexer (120), then is converted into data of 4 bit width and 10 Gbps by a 8:4 multiplexer (130), further is converted into data of 2 bit width and 20 Gbps by a 4:2 multiplexer (140) and is converted into serial data of by a 2:1 multiplexer (170) of 40 Gbps. Then, 40 Gbps data is externally outputted via a final stage buffer (180).
Next, data conversion by the multiplexers of the data transmitting circuit and data transmission/reception between the multiplexers, shown in FIG. 1 are described with reference to FIG. 2, using conversion between the 4:2 multiplexer (140) and the 2:1 multiplexer (170) as an example.
Four bits, DT_IN[0], DT_IN[1], DT_IN[2] and DT_IN[3] which are inputted from the former stage 8:4 multiplexer are received by the first stage latch circuits (141, 143, 151 and 153) of the 4:2 multiplexer (140) in synchronization with a 10 GHz clock CLK_B obtained by the frequency divider (210) for dividing into two a 20 GHz clock CLK_A supplied to the later stage 2:1 multiplexer (170).
Then DT_IN[0] and DT_IN[2] are supplied to a selector (146) via the latch circuit (142) and the latch circuits (144 and 145), respectively, and DT_IN[1] and DT_IN[3] are supplied to a selector (156) via the latch circuit (152) and the latch circuits (154 and 155), respectively.
The selectors (146 and 156) select DT_IN[0] and DT_IN[1], respectively, when the clock CLK_B rises up and select DT_IN[2] and DT_IN[3], respectively, when the clock CLK_B falls down. Therefore, as the output DT of the selector (146), two pieces of serial data, DT_IN[0] and DT_IN[2], of speed twice as high as 10 GHz can be obtained. For the output DTX of the selector (156), an analogous output can be obtained.
DT and DTX, being the outputs of the 4:2 multiplexer (140) are received by latch circuits (171 and 173) of the 2:1 multiplexer (170) in synchronization with the 20 GHz clock CLK_A, are supplied to a selector (176) via a latch circuit (172) and latch circuits (174 and 175), are selected in the selector (176) in synchronization with the rising-up and falling-down, respectively of the clock CLK_A and are outputted as the output signals DT_OUT of a transmitting circuit.
FIG. 3 is a timing chart in the case where data is normally transmitted/received between the 4:2 multiplexer (140) and the 2:1 multiplexer (170) shown in FIG. 2.
The clock CLK_A regulates the data receiving timing of the later stage 2:1 multiplexer. The clock CLK_B regulates the data output timing of the former stage 4:2 multiplexer, and is a divided clock synchronous with the rising-up edge of the clock CLK_A. When the clock CLK_B synchronous with the rising-up of the clock CLK_A rises up, data is outputted from the 4:2 multiplexer (140). The 2:1 multiplexer (170) receives this data when the clock CLK_A rises up in a subsequent cycle. In design, this timing chart must be realized under conditions in consideration of process unevenness and power voltage/temperature fluctuations. In the case of the prior art, the timing chart shown in FIG. 3 is realized by shortening the physical distance between multiplexers and also devising the circuit configurations of a multiplexer and a frequency divider.
However, in the example of a high-speed transmitting circuit for finally outputting data of 40 Gbps speed shown in FIG. 1, it is becoming difficult to surely transmit/receive data between multiplexers. FIG. 4 is a timing chart in the case where data is not normally transmitted/received between multiplexers. As shown in FIG. 4, if there is the displacement of received data in the rising-up timing of the clock CLK_A as shown in FIG. 4, the first stage latch circuits (171 and 173) of the 2:1 multiplexer (170) can neither correctly latch data nor the 2:1 multiplexer (170) can correctly receive it.
The prior art of the data transmission/reception between LSIs or the like are disclosed by the following patent references 1-3 and non-patent reference 1. The prior art disclosed by patent references 1 and 2 is one obtained by applying a circuit technology generally called Delay-Locked Loop (DLL). The phase relationship between output data and an output clock is adjusted by a data transmitting circuit in such a way that data can be surely received by a data receiving circuit. However, if a transfer distance increases or a transfer rate increases, it becomes difficult for the data receiving circuit to surely receive data, due to process unevenness and power voltage/temperature fluctuations.
The data transmitting/receiving technology disclosed by patent reference 3 and non-patent reference 1 adjust the phase of a clock for regulating the data receiving timing of the data receiving circuit for output data from the data transmitting circuit. Therefore, if only data reception is considered, data can be surely received by the data receiving circuit. However, if the speed of a clock frequency becomes high, it is not preferable to adjust a clock on the receiving side when taking into consideration the process of the data receiving circuit after receiving data and the accuracy of the multiplexer output of the transmitting circuit shown in FIG. 10.
Patent reference 1: Japanese Published Patent Application No. H10-112182
Patent reference 2: Japanese Published Patent Application No. 2004-145999
Patent reference 3: Japanese Published Patent Application No. H10-228449
Non-patent reference 1: Yasutaka Tamura and Kotaro Goto, “High-speed Signal Transmission Technology: Synfinity II”, Fujitsu, vol. 50, No. 4 pp. 235-241 (July 1999).